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2. Explanation of new features


There are now 8 bitplanes instead of 6. In single playfield modes they can
address 256 colors instead of 64. As long as the memory architecture can
support the bandwidth, all 8 bitplanes are available in all 3 resolutions
In the same vein, 4+4 bitplane dualplayfield is available in all 3
resolutions, unless bitplane scan-doubling is enabled, in which case
both playfields share the same bitplane modulus register. Bits 15 thru 8 of
BPLCON4 comprise an 8 bit mask for the 8 bitplane address, XOR`ing the
individual bits. This allows the copper to exchange color maps with a
single instruction.

BPLCON1 now contains an 8 bit scroll value for each of the playfields.
Granularity of scroll now extends down to 35nSec.(1 SHRES pixel), and
scroll can delay playfield thru 32 bus cycles. Bits BPAGEM and BPL32
in new register FMODE control size of bitplane data in BPL1DAT thru BPL8DAT.

The old 6 bitplane HAM mode, unlike before, works in HIRES and SHRES

As before bitplanes 5 and 6 control it`s function as follows:

        | BP6 | BP5 |   RED  |  GREEN | BLUE             |
        | 0   | 0   | select new base register (1 of 16) |
        | 0   | 1   |  hold  |  hold  | modify           |
        | 1   | 0   | modify |  hold  |  hold            |
        | 1   | 1   |  hold  | modify |  hold            |

There is a new 8 bitplane HAM (Hold and Modify) mode. This mode is invoked
when BPU field in BPLCON0 is set to 8 , and HAMEN is set. Bitplanes 1 and 2
are used as control bits analagous to the function of bitplanes 5 and 6 in
6 bitplane HAM mode:

        | BP2 | BP1 |   RED  |  GREEN | BLUE             |
        | 0   | 1   | select new base register (1 of 64) |
        | 0   | 1   |  hold  |  hold  | modify           |
        | 1   | 0   | modify |  hold  |  hold            |
        | 1   | 1   |  hold  | modify |  hold            |

Since only 6 bitplanes are available for modify data, the data is placed in
6 MSB. The 2 LSB are left unmodified, which allows creation of all
16,777,216 colors simultaneously, assuming one had a large enough screen
and picked one`s base registers judiciously. This HAM mode also works in
HIRES and SHRES modes.

For compatibility reasons EHB mode remains intact. Its existence is rather
moot in that we have more than enough colors in the color table to replace
its functionality. As before, EHB is invoked whenever SHRES = HIRES =
HAMEN= DPF = 0 and BPU = 6. Please note that starting with ECS DENISE
there is a bit in BPLCON2 which disables this mode (KILLEHB).

Bits PF2OF2,1,0 in BPLCON3 determine second playfield`s offset into the
color table. This is now necessary since playfields in DPF mode can have up
to 4 bitplanes. Offset value are as defined in register map.

BSCAN2 bit in FMODE enables bitplane scan-doubling. When V0 bit of DIWSTRT
matches V0 of vertical beam counter, BPL1MOD contains the modulus for the
display line, else BPL2MOD is used. When scan-doubled both odd and even
bitplanes use the same modulus on a given line, whereas in normal mode odd
bitplanes used BPL1MOD and even bitplanes used BPL2MOD. As a result Dual
Playfields screens will probably not display correctly when scan-doubled.


Bits SPAGEM and SPR32 in FMODE whether size of sprite load datain
SPR0DATA(B) thru SPR7DATA(B) is 16,32, or 64 bits, analagous to bitplanes.
BPLCON3 contains several bits relating to sprite behavior. SPRES1 and
SPRES0 control sprite resolution, whether they conform to theECS standard
or override tp LORES,HIRES,or SHRES. BRDRSPRT, when high,allows sprites to
be visible in border areas. ESPRM7 thru ESPRM4 allow relocation of the even
sprite color map. OSPRM7 thru OSPRN4 allow relocation of the odd sprite
color map. In the case of attached sprites OSPRM bits are used.

SSCAN2 bit in FMODE enables sprite scan-doubling. When enabled, individual
SH10 bits in SPRxPOS registers control whether or not a given sprite is to
be scan-doubled. When V0 bit of SPRxPOS register matches V0 bit of vertical
beam counter, the given sprite`s DMA is allowed to proceed as before. If
the don`t match, then sprite DMA is disabled and LISA reuses the sprite
from the previous line. When sprites are scan-doubled, only the position
and control registers need be modified by the programmer; the data
registers need no modification.

NOTE: Sprite vertical start and stop positions must be of the same parity,
i.e. both odd or even.


RST_pin resets all bits in all registers new to AA. These registers include:

ECSENA bit (formerly ENBPLCN3) is used to disable those register bits in
BPLCON3 that are never accessed by old copper lists, and in addition are
required by old style copper lists to be in their default
settings.Specifically ECSENA forces the following bits to their default low

CLXCON2 is reset by a write to CLXCON, so that old game programs will be
able to correctly detect collisions.

DIWHIGH is reset by writes to DIWSTRT or DIWSTOP. This is interlock is
inhertied from ECS Denise.


Lots of new genlock features were added to ECS DENISE and arecarried over
to LISA. ZDBPEN in BPLCON2 allows any bitplane, selected by ZDBPSEL2,1,0,to
be used as a transparency mask (ZD pin mirrors contents of selected
bitplane). ZDCTEN disables the old COLOR00 is transparent mode, and allows
the bit31 position of each color in the color table to control
transparency.ZDCLKEN generates a 14MHz clock synchronized with the video
data that can be used by video post-processors. Finally, BRDNTRAN in
BPLCON3 generates an opaque border region which can be used to frame live

Color Lookup Table

The color table has grown from 32 13-bit registers to 256 25-bit registers.
Several new register bits have been added to BPLCON3 to facilitate loading
the table with only 32 register addresses. LOCT, selects either the 16 MSB
or LSB for loading. Loading the MSB always loads the LSB as well for
compatibility, so when 24 bit colors are desired load LSB after MSB.
BANK2,1,0 of 8 32 address banks for loading as follows:

        |  0    |   0   |   0   |  COLOR00 - COLOR1F   |
        |  0    |   0   |   1   |  COLOR20 - COLOR3F   |
        |  0    |   1   |   0   |  COLOR40 - COLOR5F   |
        |  0    |   1   |   1   |  COLOR60 - COLOR7F   |
        |  1    |   0   |   0   |  COLOR80 - COLOR9F   |
        |  1    |   0   |   1   |  COLORA0 - COLORBF   |
        |  1    |   1   |   0   |  COLORC0 - COLORDF   |
        |  1    |   1   |   1   |  COLORE0 - COLORFF   |

RDRAM bit in BPLCON2 causes LISA to interpret all color table accesses as
Note: There is no longer any need to "scramble" SHRES color table entries.
This artifice is no longer required and pepole who bypass ECS graphics
library calls to do their own 28MHz graphics are to be pointed at and
publicly humiliated.


A new register CLXCON2 contains 4 new bits. ENBP7 and ENBP6 are the enable
bits for bitplanes 7 and 8, respectively. Similarly, MVBP7 and MPBP8 are
their match value bits. CLXDAT is unchanged.

Horizontal Comparators

All programmable comparators with the exception of VHPOSW have 35nSec
resolution.: DIWHIGH, HBSTOP, SPRCTL, BPLCON1. BPLCON1 has additional
high-order bits as well. Note that horizontal bit position representing
140nSec resolution has been changed to 3rd least significant bit,where
before it used to be a field`s LSB, For example, bit 00 in BPLCON1 used to
be named PF1H0 and now it`s called PF1H2.

Coercion of 15KHz to 31KHz:

We have added new hardware features to LISA to aid in properly displaying
15KHz and 31KHz viewports together on the same 31KHz display. LISA can
globally set sprite resolution to LORES, HIRES, or SHRES.
LISA will ignore SH10 compare bits in SPRxPOS when scan-doubling, thereby
allowing ALICE to use these bits individually set scan-doubling.