The number of clock periods periods shown in this table includes the time to
fetch immediate operands, perform the operations, store the results and read 
the next operation. The number of bus read and write cycles is shown in
parenthesis as (r/w). The number of clock periods and the number of read and 
write cycles must be added respectively to those of the effective address
calculation where indicated.


		Immediate Instruction Execution Times

instruction	size		op #,Dn		op #,An		op #,M

ADDI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
ADDQ		byte,word	 4(1/0)		8(1/0) *	 8(1/1) +
		  long		 8(1/0)		8(1/0)		12(1/2) +
ANDI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/1) +
CMPI		byte,word	 8(2/0)		  -		 8(2/0) +
		  long		14(3/0)		  -		12(3/0) +
EORI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
MOVEQ		  long		 4(1/0)		  -		   -
ORI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
SUBI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
SUBQ		byte,word	 4(1/0)		8(1/0) *	 8(1/1) +
		  long		 8(1/0)		8(1/0)		12(1/2) +

	+ Add effective address calculation time
	* word only