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NAME
AND -- Logical AND
SYNOPSIS
AND <ea>,Dn
AND Dn,<ea>
Size = (Byte, Word, Long)
FUNCTION
Performs a bit-wise AND operation with the source operand and
the destination operand and stores the result in the destination.
The size of ther operation can be specified as byte, word, or long.
The contents of an address register may not be used as an operand.
FORMAT
-----------------------------------------------------------------
|15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|-----------|-----------|-----------|-----------|
| 1 | 1 | 0 | 0 | REGISTER | OP-MODE | MODE | REGISTER |
----------------------------------------=========================
<ea>
OP-MODE
Byte Word Long
000 001 010 (Dn)AND(<ea>)-> Dn
100 101 110 (<ea>)AND(Dn)-> <ea>
REGISTER
One of the 8 datas registers
If <ea> is source, allowed addressing modes are:
--------------------------------- -------------------------------
|Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register|
|-------------------------------| |-----------------------------|
| Dn |000 |N° reg. Dn| | Abs.W |111 | 000 |
|-------------------------------| |-----------------------------|
| An | - | - | | Abs.L |111 | 001 |
|-------------------------------| |-----------------------------|
| (An) |010 |N° reg. An| | (d16,PC) |111 | 010 |
|-------------------------------| |-----------------------------|
| (An)+ |011 |N° reg. An| | (d8,PC,Xi) |111 | 011 |
|-------------------------------| |-----------------------------|
| -(An) |100 |N° reg. An| | (bd,PC,Xi) |111 | 011 |
|-------------------------------| |-----------------------------|
| (d16,An) |101 |N° reg. An| |([bd,PC,Xi],od)|111 | 011 |
|-------------------------------| |-----------------------------|
| (d8,An,Xi) |110 |N° reg. An| |([bd,PC],Xi,od)|111 | 011 |
|-------------------------------| |-----------------------------|
| (bd,An,Xi) |110 |N° reg. An| | #data |111 | 100 |
|-------------------------------| -------------------------------
|([bd,An,Xi]od) |110 |N° reg. An|
|-------------------------------|
|([bd,An],Xi,od)|110 |N° reg. An|
---------------------------------
If <ea> is destination, allowed addressing modes are:
--------------------------------- -------------------------------
|Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register|
|-------------------------------| |-----------------------------|
| Dn | - | - | | Abs.W |111 | 000 |
|-------------------------------| |-----------------------------|
| An | - | - | | Abs.L |111 | 001 |
|-------------------------------| |-----------------------------|
| (An) |010 |N° reg. An| | (d16,PC) | - | - |
|-------------------------------| |-----------------------------|
| (An)+ |011 |N° reg. An| | (d8,PC,Xi) | - | - |
|-------------------------------| |-----------------------------|
| -(An) |100 |N° reg. An| | (bd,PC,Xi) | - | - |
|-------------------------------| |-----------------------------|
| (d16,An) |101 |N° reg. An| |([bd,PC,Xi],od)| - | - |
|-------------------------------| |-----------------------------|
| (d8,An,Xi) |110 |N° reg. An| |([bd,PC],Xi,od)| - | - |
|-------------------------------| |-----------------------------|
| (bd,An,Xi) |110 |N° reg. An| | #data | - | - |
|-------------------------------| -------------------------------
|([bd,An,Xi]od) |110 |N° reg. An|
|-------------------------------|
|([bd,An],Xi,od)|110 |N° reg. An|
---------------------------------
AND between two datas registers is allowed if you consider the
syntax where Dn is at destination's place.
If you use this instruction with an immediate data, it does the
same as instruction ANDI.
RESULT
X - Not affected
N - Set if the most-significant bit of the result was set. Cleared
otherwise.
Z - Set if the result was zero. Cleared otherwise.
V - Always cleared.
C - Always cleared.
SEE ALSO
ANDI